1. Field of the Invention
The current invention generally relates to integrated circuit design and fabrication. More specifically, the current invention relates to silicide semiconductor production processes.
2. Description of the Related Art
Continuous improvements in the design and fabrication of microelectronic devices have led to smaller and faster computing devices capable of solving increasingly complex problems. Rapid gains in the performance of these devices have enabled technology users to solve increasingly complex problems. However, increasingly complex problems have demanded larger amounts of computing power, and as a result, more microelectronic devices such as field effect transistors (FETs) are needed to perform the necessary computations. Moreover, while the demand for computing power has increased the transistor counts on computer chips, physical chip size has been reduced or held constant thus complicating design and fabrication processes.
Semiconductor chips are composed of several basic elements: a collection of active components such as FETs, signal conductors such as metal or suitably doped polysilicon that transmit electrical signals between these components, and insulating (or “dielectric”) material that separates the metal traces from one another. To produce consistent batches of computer chips, a formal production process is employed containing four high-level steps: microlithography, implantation, deposition and etching. Modern computer chips currently contain millions of transistors that are printed during the microlithography stage using a light source that ranges in wavelength from 130 to 90 nanometers. Each transistor is then implanted with, e.g., boron or phosphorus to effectively dope the transistor creating a device capable of behaving as a conductor or an insulator based on its electrical properties and the voltage applied. The ability to switch between a conductor and an insulator facilitates the binary behavior necessary for modern computing. Reducing the size of the field effect transistor lowers the voltage necessary to switch between a conductor and an insulator. Furthermore, smaller FETs that require less voltage also require less time to switch. Thus, it is desirable to create smaller FETs because of the performance gains and cost savings resulting from smaller feature sizes.
The production methods used to fabricate field effect transistors are well known in the art of manufacturing microelectronic devices. The methods known are expensive processes that require a significant number of steps and generally require over a month to complete. In a mass production environment, eliminating one or more steps can result in expense savings and increased profits for both the manufacturer and the consumer. As a result, large amounts of research and development are directed at eliminating steps of the fabrication process and improving the design of FETs.
Referring to FIG. 1, a silicon on insulator FET is comprised of a polysilicon shape 8 positioned on a silicon substrate patterned with oxide areas and doped silicon areas. Portions of the silicon have been doped and comprise a source 5 and a drain 6 of the FET, which are individually positioned on either side of the polysilicon shape 8.
The electrical signal generated by the switching of the FET is transmitted through separate couplings created on both the source 5 and the drain 6. These couplings historically use vias, which are holes formed in the layers of the chip. The vias are filled with a conductive material such as tungsten, aluminum, or copper permitting the signals to be communicated from the source 5 or drain 6 of the FET to other microelectronic devices using signal conductors such as metals previously mentioned. FETs are produced using a self-aligned process to block implants into source and drain regions of a silicon area.
One step in the process of making FETs involves aligning the polysilicon with the silicon area to ensure that the FETs operate according to preset specifications. The alignment process is never perfect; however, the overlay alignment measurement is critical for FET operation and must be tightly and measurably controlled during manufacture. Currently, there is no accurate measurement of this important parameter that can be done effectively and at low cost. U.S. Pat. No. 5,699,282 uses a technique of alignment measurement that performs electrical measurements. The technique employed requires vias and metal interconnections. Vias and metal interconnections consume valuable design space, which could be used more efficiently for chip test function. Metal interconnection uses up valuable space that is needed to interconnect logical blocks on the semiconductor chip. Therefore, a need exists to create an accurate process that properly measures alignment errors that occur during the manufacture of the semiconductor chip.
Modern semiconductor processes include a silicide step, in which a suitable metal, such as titanium, is deposited on the chip and the chip is heated forming silicide on the sources, drains, and polysilicon which provides those areas with a lower electrical resistance. An example of this prior art design is illustrated in FIG. 1 where source 5 has a source silicide portion 10, drain 6 has a drain silicide portion 13, and polysilicon shape 8 has a polysilicon shape silicide portion 12.
Another particular step in the process of creating FETs involves the creation of a spacer 9A, 9B, which ensures separation of silicide portions of the polysilicon shape 8 from the silicon areas (source 5 and drain 6) to prevent electrical silicide bridging (shorts) between the polysilicon shape 8 and the source 5 and drain 6. The spacer 9A, 9B is generally a silicon oxide composition or other dielectric material. In U.S. Pat. No. 4,983,544, a method is proposed to facilitate the formation of an electrical bridge using silicide as a bridge contact rather than a via or other metal interconnect. It is advantageous to have different interconnection alternatives that give circuit designers additional flexibility when designing circuit layouts. However, U.S. Pat. No. 4,983,544 achieves this flexibility only by providing a mask and subsequent etching steps for selectively etching portions of spacers, thereby exposing corresponding vertical surfaces of polysilicon shapes to a subsequent silicide process, forming an electrically conducting silicide bridge between the polysilicon shape and the silicon area. Controlling precision in the etching process is a difficult task, and also requires that an additional etching step be inserted into the transistor fabrication process requiring more time and additional etching materials expenses.
Also, it is presently not desirable and considered a groundrule design violation to form a polysilicon shape containing a small angle such that when a spacer is formed on a polysilicon shape, a portion of a vertical surface of the polysilicon shape becomes silicided and can become shorted to the silicon area. If such a design were permitted to exist in the current state of the art, FET designs would not function as designed due to shorts that would occur between the exposed polysilicon and the silicon area.
It would be advantageous to have an alternative method to the traditional via coupling that facilitates the interconnection of microelectronic devices while simultaneously reducing circuit layout constraints and fabrication requirements. Therefore, a need exists to create an alternative method to interconnect microelectronic devices that does not require a via coupling between the metal layer and silicon areas. Furthermore, it is desirable to compact more microelectronic devices into a smaller area. A need also exists to decrease the amount of space required to accommodate a specified number of microelectronic devices and the accompanying metal interconnects. Simplified contact structures, which require less space will result in higher chip densities, lower production costs, increased performance, and reduced power consumption.